Reports from Taiwanese media indicate that Taiwan Semiconductor Manufacturing (TSM.US) is targeting a doubling of its chip packaging (CoWoS) capacity in 2028 compared to 2026 levels. CoWoS is the leading packaging technology for AI GPUs, widely adopted by major enterprises such as NVIDIA. The reports also note that this capacity expansion comes as existing capacity constraints are causing spillover effects to other companies like UMC and Amkor.

Intel is expected to reach a CoWoS wafer capacity of 45,000 wafers per month by 2028. The robust demand for TSMC's CoWoS technology and the resulting supply shortage have prompted other suppliers and technologies to emerge. Intel's EMIB-T technology is frequently mentioned in supply chain reports. EMIB-T's architecture differs significantly from CoWoS; it relies on pathways and circuits called "bridges" embedded within an organic substrate, with components like logic and memory chips placed atop these bridges. CoWoS, on the other hand, uses an interposer to enable communication between memory chips, logic chips, and the main computer. This interposer consists of vertical circuits known as silicon vias (TSVs), whose high-density design enables higher bandwidth and lower latency, ideal for high-performance AI chips from companies like NVIDIA.

Analysts cited by a Taiwanese media outlet suggest that TSMC plans to increase its CoWoS wafer packaging capacity to 260,000 wafers per month by the end of 2028, compared to an expected 130,000 wafers per month this year. Specifically, the expansion will primarily focus on TSMC's Arizona facility in the United States and the AP7 plant in Taiwan. While the Arizona plant can produce the latest chips, these must be air-freighted to Taiwan for packaging since all of the company's packaging capacity is located there.

Analysts have also speculated on Intel's EMIB-T capacity. If converted to 12-inch wafer equivalents comparable to CoWoS, capacity could range between 15,000 and 20,000 wafers per month by 2027, and 40,000 to 45,000 wafers per month by 2028. EMIB-T's architecture makes it better suited for custom AI chips, such as those designed by Google and Amazon. Taiwanese analysts added that TSMC's CoWoS shortage has led to increased demand for services from other packaging companies like Amkor, UMC, and ASE.

Understanding the CoWoS Capacity Battle

If the defining theme of the semiconductor industry's past decade was "Moore's Law," the current buzzword is undoubtedly advanced packaging. As large model parameters surge from tens of billions to trillions, relying solely on process miniaturization to boost computing power is approaching physical limits. An AI chip must accommodate massive compute units and high-bandwidth memory simultaneously, making traditional 2D packaging inadequate. Consequently, the HBM+CoWoS combination has become a near-mandatory choice for high-end AI chip makers. From NVIDIA's Blackwell architecture GPUs to AMD's MI series accelerators and cloud vendors' custom training chips—whoever secures sufficient CoWoS capacity can truly establish a foothold in the AI computing race. A "positioning battle" over TSMC's CoWoS packaging capacity is quietly unfolding among global chip giants.

Why CoWoS Is Indispensable

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's 2.5D advanced packaging technology. Simply put, instead of directly soldering chips and memory onto a substrate, it places compute chips like GPUs/ASICs and HBM memory chips side-by-side on an interposer using high-density TSVs and micro-bumps. Dense micro-circuits within the interposer enable high-speed chip-to-chip interconnectivity, and the entire package is then mounted onto a substrate. The need for this arises because traditional PCB circuit board line widths are too coarse, limiting signal transmission distance and speed. A GPU often needs to connect to multiple HBM stacks with bandwidth requirements reaching several terabytes per second—only the ultra-fine lines of a silicon interposer can handle such massive transmission loads.

TSMC officially launched CoWoS in 2011, and after multiple iterations, it now offers three variants: CoWoS-S (full silicon interposer), CoWoS-R (RDL interposer), and CoWoS-L (local silicon bridge + organic substrate). CoWoS-L is the current mainstream solution, replacing ultra-large monolithic silicon interposers with "local silicon bridges" to reduce warpage and cost while supporting larger package sizes and more HBM stacks. The core advantages of this architecture are clear: bandwidth improvements (HBM and GPU interconnect directly via the silicon interposer, offering bandwidth tens of times greater than traditional DDR, resolving the "memory wall" issue in AI training); lower power consumption (significantly shortened signal transmission distances reduce data movement power); and higher integration (multiple chiplets and HBM stacks can work within a single package, breaking through single-chip area limits). Without CoWoS, today's trillion-parameter large model training chips might not exist.

Who Is Competing for CoWoS?

According to Morgan Stanley's supply chain research forecasts, global CoWoS wafer demand from key customers will total approximately 1.384 million wafers in 2026, surging to 2.682 million by 2027—nearly doubling in two years. The participants in this capacity battle have expanded from GPU vendors alone to the entire AI computing supply chain.

NVIDIA remains the dominant player but its share is being diluted. NVIDIA's CoWoS capacity demand is 780,000 wafers in 2026, jumping to 1.2 million in 2027, securing the top spot. From Hopper to Blackwell and the latest Rubin architecture, each generation of GPUs is deeply tied to TSMC's CoWoS-L process. CoWoS-R is mainly used for NVIDIA's Vera CPU production, with expected shipments of 5.75 million units, indicating nearly doubled Vera CPU shipments and over 100,000 wafers of CoWoS-R demand. CoWoS-S is used for Quantum and Spectrum switch chips. Overall, NVIDIA alone accounts for over half of TSMC's CoWoS capacity. Notably, NVIDIA's share of total demand will decline from approximately 56% in 2026 to around 45% in 2027—absolute value is rising, but the share is being diluted. This signals that the CoWoS market is shifting from NVIDIA's dominance to a multi-player landscape.

AMD is the biggest dark horse in 2027, with growth nearly matching NVIDIA. AMD's CoWoS capacity demand is only 130,000 wafers in 2026, soaring to 530,000 in 2027—an increase of 400,000 wafers, nearly on par with NVIDIA's 442,000. The main drivers are AMD's MI series AI server chip volume ramp-up and the large-scale adoption of 3D V-Cache and chiplet architectures, tripling AMD's CoWoS demand in one year (307% growth). In 2027, AMD's key product is the MI455, with small-scale production of MI500 (Arcadia) at year-end. For AMD's Venice CPU, the company relies on non-TSMC CoWoS processes from ASE/SPIL and Amkor, with capacity surging from 50,000 to 270,000 wafers, corresponding to an estimated 6.75 million CPUs driven by agentic AI demand. Interestingly, Xilinx's 10,000-wafer demand remains flat after being acquired by AMD, suggesting all growth comes from AMD's own product line explosion, while FPGA product lines' CoWoS demand appears saturated or shifting to other packaging methods.

Broadcom shows steady growth in networking chips. Broadcom's capacity demand is 300,000 wafers in 2026, ranking second in CoWoS demand; in 2027, it is expected to grow to 484,000 wafers (61% year-over-year), overtaken by AMD to third place. Unlike the former two, Broadcom's core products are high-end networking switch chips rather than GPUs. The surge in demand for 800G and 1.6T switches in AI clusters is driving Broadcom's Tomahawk series to fully adopt CoWoS advanced packaging. Additionally, Broadcom assists in designing and manufacturing Google TPU v7 (Ironwood) and v8i (SunFish) chips, consuming CoWoS capacity.

MediaTek emerges unexpectedly. MediaTek's demand jumps from 40,000 to 180,000 wafers, a 350% increase—the most surprising highlight on this list. This traditional smartphone chip giant is aggressively entering the AI accelerator market, with cloud and edge ASIC chips beginning to adopt CoWoS at scale, achieving the highest growth rate among all top customers. Suppliers reveal that MediaTek's ASIC business primarily stems from Google's TPU v8t (ZebraFish) chips, estimated to correspond to 3.6 million units shipped.

AWS is steadily increasing cloud vendor self-developed chips. AWS's combined demand from its two self-developed chip lines (Annapurna and Alchip) grows from 88,000 to 126,000 wafers, reflecting the continuous iteration of Trainium training chips and Inferentia inference chips. This represents cloud vendors' determination to reduce dependence on a single GPU supplier, though growth is more moderate compared to leading vendors.

Marvell and GUC see custom ASIC undercurrents. Marvell grows from 17,000 to 64,000 wafers (276% growth), and GUC from 14,000 to 60,000 (329% growth). The surge in both reflects a trend: the custom AI ASIC market is exploding. Marvell's DPUs and AI networking chips, along with GUC's ASIC design services, are consuming significant CoWoS capacity. More internet companies are choosing to self-develop AI chips, all requiring design service providers to connect with TSMC's packaging capacity.

Cisco remains stagnant in traditional tracks. Cisco's demand only grows from 5,000 to 6,000 wafers, reflecting the limited pull of traditional networking equipment and mid-to-low-end FPGAs on high-end CoWoS. This segment is being increasingly squeezed by AI-related demand.

Overall, CoWoS demand structure is undergoing profound changes: the AI GPU camp forms the baseline (NVIDIA + AMD + Broadcom occupy the vast majority of capacity); ASIC and networking chips are the new growth drivers (MediaTek, Marvell, GUC benefit from AI switch and high-speed interconnect chip demand, with packaging demand doubling at growth rates far exceeding industry averages); cloud vendor self-developed chips are the long-term variable (though currently modest in scale, cloud-based custom large model chips continue to expand, representing the trend toward supply chain decentralization); traditional FPGA/networking equipment (Xilinx, Cisco) shows stagnant demand with limited pull from high-end CoWoS. From an industry aggregate perspective, global CoWoS capacity demand from key customers grows from approximately 1.384 million wafers in 2026 to 2.682 million in 2027, an overall increase of approximately 94%—nearly doubling in two years, confirming Morgan Stanley's view of high growth in the advanced packaging sector. When all players crowd into the same track, capacity shortages naturally surface.

Capacity Bottleneck: TSMC Is Running Fast, But Not Fast Enough

TSMC, well aware of CoWoS's strategic value, is expanding capacity aggressively. According to data, CoWoS monthly capacity was only around 10,000 wafers in 2022, approaching 70,000 in 2025. With TSMC and its partners actively expanding, CoWoS monthly capacity is expected to reach a record 120,000-140,000 wafers by 2026, further increasing to 170,000 per month in 2027 (some plans show 200,000 per month by end-2027), with expansion concentrated in Tainan and Chiayi, significantly exceeding previous levels. While expanding CoWoS, TSMC is actively advancing its industry-leading CoPoS (Chip on Panel on Substrate) panel-level packaging technology, with pilot production lines expected to complete commissioning by June 2026 and mass production as early as 2028-2029 to address large-size chip packaging needs.

Beyond TSMC, other camps are also actively expanding: by end-2027, non-TSMC camps (ASE/SPIL, Amkor, etc.) are expected to expand CoWoS capacity to 80,000 wafers per month. ASE/SPIL grows from 30,000 wafers per month at end-2026 to 50,000, while Amkor grows from 20,000 to 30,000, both focusing on CoWoS-L and CoWoS-R. The industry supply structure is shifting from TSMC's single-point dominance to parallel expansion across foundries and OSATs. UBS expects CoWoS industry monthly capacity to grow from 160,000 wafers at end-2026 to 250,000 by end-2027, an annual increase of about 56%. Behind this expansion, Rubin, AMD Venice, Google TPU, and Amazon Trainium are all simultaneously increasing packaging demand. Meanwhile, over the next five years, TSMC CoWoS will continue to expand in size annually to integrate more logic and HBM. In 2026, the world's largest 5.5x reticle-size CoWoS was produced with yields exceeding 98%; a 14x reticle-size CoWoS integrating 20 HBM stacks will enter mass production in 2028, and a version integrating 24 HBM stacks larger than 14x reticle will be ready by 2029. Supply chain sources reveal that not only is CoWoS demand strong, but TSMC's SoIC and CoPoS progress is also rapid, extending equipment supply chain order visibility to 2030. For example, TSMC's SoIC capacity is continuously expanding—previously estimated at 10,000 wafers per month rising to 20,000 in 2027, the latest reports suggest an upward adjustment to 50,000, with NVIDIA booking substantial capacity.

However, new capacity will soon face a larger order pool. According to UBS estimates, total CoWoS capacity demand will grow from 1.307 million wafers in 2026 to 2.475 million in 2027 (Morgan Stanley forecasts 2.682 million), an annual growth of about 89%, significantly outpacing industry monthly capacity growth. Supply chain sources indicate the current CoWoS supply-demand gap is approximately 20%, expected to narrow to about 10% by end-2026. Other institutions estimate the capacity gap could widen to approximately 700,000 wafers in 2027, exceeding 30%. Supply chain suppliers point out that even with CoWoS monthly capacity raised to 200,000+ wafers, meeting all customer orders remains challenging, compounded by risks from expansion, monopoly, and US domestic manufacturing. Many customers have moved from near-exclusive reliance on TSMC to listing ASE, SPIL, and Amkor as overflow order targets, establishing second-source advanced packaging pathways.

Other reasons capacity expansion cannot keep pace with demand include: high process thresholds (CoWoS involves large-size silicon interposers, TSV vias, micro-bump bonding, and other precision processes requiring time for yield ramp-up); long equipment supply chains (bonding and inspection equipment delivery cycles exceed one year—money alone cannot expedite expansion); and CoWoS is often tied to HBM—if SK Hynix and Samsung's HBM capacity lags, CoWoS capacity cannot ship regardless of size. This creates an awkward situation: TSMC's CoWoS capacity remained fully utilized from 2024-2026, with order visibility extending to 2027. Under these conditions, major chip makers negotiate with TSMC over a year in advance to lock in capacity, with industry norms around "capacity-grabbing" priorities emerging. Another concern: while CoWoS packaging demand rises, leading-edge process technology is also tightening. UBS notes cloud AI products' share of TSMC's N3 demand will rise from 35% in 2026 to 72% in 2027, with average capacity utilization around 108% and 109% respectively over two years. Rubin, Vera CPU, Google TPU, and Trainium all require N3 wafers before entering the CoWoS stage. Customer structure is rapidly changing: NVIDIA's share of TSMC's N3 capacity is expected to rise from 10% in 2026 to 30% in 2027, Broadcom from 10% to 16%; meanwhile, Apple's share drops from 38% to 14%. While consumer electronics demand persists, cloud AI is clearly increasing dual occupancy of advanced process and back-end packaging. Whether CoWoS supply can keep up depends on all these stages ramping at the same pace. The 250,000-wafer monthly industry capacity target for end-2027 requires advanced process wafer supply, OSAT full-process yields, bonding and metrology equipment delivery to be fulfilled simultaneously, while waiting for Rubin, Venice, and TPU to ramp as planned. With demand coming from more customers, CoWoS has moved away from dependence on a single GPU cycle but increased complexity in product mix and scheduling. Recent industry voices suggest TSMC has yet to finalize equipment supplier order allocation, leaving suppliers anxious about potential price-cutting competition, while equipment order-to-delivery timelines take at least 7-9 months, raising concerns about timely delivery.

More challenging than capacity are the technical and cost bottlenecks. CoWoS's silicon interposer faces three major issues: high cost, size limitations, and warpage susceptibility. A 12-inch silicon interposer costs over $100 per piece, accounting for more than half of total packaging costs. As AI chips grow larger—NVIDIA's B200 package area has reached 3-4 times the load limit of a single silicon interposer—the size bottleneck of silicon interposers has become unavoidable. The next-generation Rubin GPU is even larger, currently relying on "local silicon bridge + organic substrate" solutions as a stopgap.

Intel and Samsung Sharpening Their Knives

CoWoS capacity tightness also creates opportunities for competitors. CoWoS is not the only answer to 2.5D packaging; competitors are accelerating their alternative solutions. Intel and Samsung, long locked in battles over advanced processes, are sharpening their knives for the massive market pie and capacity gap in advanced packaging.

Intel's EMIB and Foveros: Intel possesses its own 2.5D/3D packaging technology matrix. Among them, EMIB (Embedded Multi-die Interconnect Bridge) is actively seizing market share. Unlike CoWoS, EMIB replaces full-size interposers with locally embedded silicon bridges, enabling localized high-speed interconnect between chiplets with higher yields and significantly lower costs. Compared to CoWoS, EMIB uses only 1/3 to 1/5 of the silicon, with per-unit costs 30%-50% lower. EMIB-M already supports 6x reticle sizes, targeting 8-12x by 2026-2027. It carries lower thermal expansion mismatch risk, fewer warpage issues, and yields exceeding 90%. EMIB processes continue to evolve: EMIB (first generation) uses basic silicon bridges for general heterogeneous integration of CPU+GPU/HBM; EMIB-M (Matrix) features multi-bridge arrays, currently at 6x reticle, targeting 8-12x in 2026-2027 for ultra-large multi-chiplet AI chips; EMIB-T (Through-Silicon-Via) introduces TSVs in the silicon bridge for vertical power delivery, bringing power and signals from the package base directly to the chip, suppressing DC/AC noise crosstalk, and meeting stringent bandwidth and power requirements of AI accelerators and data center chips. Back-end yields have climbed above 90%. EMIB with glass substrate debuted in early 2026 with a 78×77mm giant package (2x standard reticle), using "10-2-10" stacking (800μm thick glass core + 10 RDL layers on each side = 20 circuit layers), targeting HPC and AI servers.

In market progress, Intel's EMIB-T packaging secured Google's next-generation TPU order in 2026; NVIDIA's next-generation GPU Feynman also plans to adopt EMIB; Meta plans to use it in 2028 CPUs; SK Hynix is collaborating with Intel to test EMIB to reduce dependence on CoWoS. Recently, Intel announced the appointment of Lee Seok-hee as Executive Vice President of Intel Foundry, responsible for advanced packaging, system integration, back-end technology development, and back-end manufacturing, reporting directly to CEO Lip-Bu Tan. The core significance is that Intel is elevating advanced packaging to a key growth point for its Foundry business. AI accelerators typically require integrating logic chips, HBM, I/O chips, and other chiplets into a single package, making packaging platform capabilities directly influential on customer decisions to adopt Intel Foundry. Strengthening back-end packaging independently helps Intel offer more complete system-level manufacturing solutions beyond 18A, 14A, and subsequent processes. For the global landscape, Intel aims not only to catch up with TSMC in front-end processes but also to attract AI ASIC, HPC, and cloud service customers through back-end technologies like EMIB, Foveros, EMIB-T, and hybrid bonding. Advanced packaging could become Intel's entry point back into high-end customer supply chains. Industry insiders note that EMIB is transitioning from a CoWoS alternative to the second pole of packaging in the AI large-chip era, with its dual-track evolution of "silicon bridge + glass substrate" constraining CoWoS's premium pricing. Foveros is Intel's true 3D stacking technology, enabling logic-on-logic stacking. As Intel's IDM 2.0 strategy advances, its packaging business has begun taking external orders, directly competing with TSMC's CoWoS and SoIC.

Samsung's I-Cube: Samsung's competitive advantage lies in its complete "turnkey" solution spanning HBM manufacturing, logic process foundry, and advanced packaging. Samsung's SAINT (Samsung Advanced Interconnect Technology) family includes I-Cube (2.5D) and X-Cube (3D) technologies. Leveraging its own HBM memory capacity, Samsung is aggressively pursuing AI chip customer packaging orders, attempting to form an integrated "memory + packaging" competitive edge. I-Cube uses silicon interposers to integrate logic chips and HBM, currently supporting integration of up to 8 HBM stacks. For next-generation HBM4, Samsung is actively advancing hybrid bonding technology to replace traditional micro-bump stacking, aiming to improve thermal dissipation and reduce package height. Samsung plans to substantially increase HBM monthly capacity to 250,000 wafers by 2026 to regain dominance in the high-performance AI accelerator market. However, industry sources note: "Customers using Samsung's 2.5D packaging platform either have very small shipment volumes or only short-term projects lasting a few months. In an era where advanced packaging determines chip performance, Samsung urgently needs to strengthen its competitiveness in this area." In response, Samsung is shifting its 2.5D packaging technology roadmap from traditional wafer-level packaging (WLP) to panel-level packaging (PLP). PLP uses square large-size panels with higher area utilization and production efficiency than circular wafers. As AI chips continue to grow in size, PLP's applicability will further improve. Samsung is advancing the transition of its Cube technology from WLP to PLP and developing "System-on-Panel (SoP)" for ultra-large chips, currently at 415mm×510mm dimensions.

Diverse Routes for Industry Players

Additionally, ASE and Amkor and other OSAT giants are developing similar 2.5D packaging solutions. While still lagging CoWoS in cutting-edge performance, they offer advantages in cost and capacity flexibility, encroaching on the mid-to-high-end market. For example, ASE's VIPack™ platform supports a full range of heterogeneous integration needs from fan-out chip packaging (FOCoS) to co-packaged optics (CPO). To address AI-driven capacity shortages, ASE plans capital expenditures exceeding $6 billion in 2025, focusing on expanding CoWoS-like capacity at Kaohsiung and Central Taiwan facilities. ASE has also demonstrated advanced silicon photonics technology, integrating optical engines directly onto packaging substrates to significantly improve data transmission efficiency within AI data centers. Amkor, as the world's second-largest OSAT, focuses on close alignment with advanced process foundries. Amkor signed a memorandum of understanding with TSMC to provide packaging and testing support at its Arizona facility, shortening wafer transpacific shipping turnaround times. Amkor's R&D priorities in high-performance computing include RDL interposer technology and bridge technologies (such as Connect-S), with several computing and networking customers in qualification phase and mass production expected in 2026. Additionally, Amkor holds significant advantages in high-density fan-out (HDFO), providing thin and efficient interconnect solutions for next-generation smartphones and automotive ADAS systems.

These routes are not purely competitive and mutually exclusive but serve different applications: high-end AI GPUs prioritize bandwidth, yield, and maturity; custom AI ASICs may prioritize cost, supply flexibility, and multi-vendor strategies; consumer electronics and edge AI products emphasize size, cost, and high-volume manufacturing capability. Looking ahead, the advanced packaging market will not remain dominated by TSMC alone but will feature multiple technology routes and multiple suppliers coexisting.

How China's Advanced Packaging Breaks Through

When advanced packaging is held by a few manufacturers, China's semiconductor industry naturally cannot stand aside. CoWoS capacity tightness and technical barriers highlight the urgency for China to accelerate breakthroughs in advanced packaging. The good news is that China is catching up with full force and is not starting from zero in advanced packaging. OSAT giants like JCET, Tongfu Microelectronics, and Hua Tian Technology have all deployed 2.5D/3D packaging and chiplet technology routes, with some products already in mass production. For example, JCET announced in June 2026 an investment of RMB 7.8 billion to build a high-end advanced packaging facility in Shanghai Lingang, focusing on four directions: 2.5D/3D stacking, HBM3e, chiplets, and CPO. Additionally, local companies like SJ Semi, Yongsilicon, and China Wafer Level CSP are enhancing local supply chain value through distinctive advanced packaging capabilities. The third phase of the National Big Fund has listed advanced packaging as a key support direction. Compared to TSMC's CoWoS, Chinese manufacturers may still lag in HBM collaboration, yield control, and customer ecosystem for the most advanced AI GPU packaging, but they offer closer proximity to local customers for domestic AI chips and specialized applications. More importantly, the proliferation of chiplet architecture provides a "lane-changing overtaking" window for the domestic industry. When chips no longer pursue extreme single-chip size but achieve high performance through multi-chiplet integration, packaging's value share will continue to rise—precisely where China's OSAT industry has deep expertise.

Final Thoughts

The CoWoS battle is far from over. TSMC expands, Intel, Samsung, and ASE chase, while domestic players strive to break through. Who ultimately prevails in the advanced packaging race will profoundly shape the AI chip landscape for the next decade. For China's industry, this is both a challenge and a historical opportunity not to be missed.